چكيده به لاتين
Abstract:
With technology scaling, the number of uncore components increases on a chip in Chip-Multiprocessors (CMPs). As the number of cores increases, power consumption becomes the main concern in Network on Chip (NoC) and Last Level Cache (LLC). Emerging technologies, such as three-dimensional integrated circuits (3D ICs) and non-volatile memories (NVMs) are among the newest solutions to the design of dark-silicon-aware multi/many-core systems. In on-chip interconnection networks, components must be activated for each access, consequently the energy of NoC increases. Although NVMs have many advantages like low leakage and high density, they suffer from shortcomings such as the limited number of write operations and long write operation latency and high energy. In this thesis, we propose two new architectures based on coding called UCA and NoS.
First architecture i.e. UCA simultaneously target the short lifetime of NVM LLC and the crosstalk problem of Through-Silicon-Vias (TSVs). This architecture identifies frequent values at runtime in order to encode these values using limited weight codes and therefore reduce the number of bit flips to minimize energy and crosstalk in NoC. Furthermore, this encoding can also improve the life of NVMs integrated into the LLC. Experimental results show that the proposed method improves energy by about 27% on average under PARSEC workloads execution. Moreover, this technique improves Average Memory Access Time by about 7% on average compared to the conventional methods with SRAM cache technology under PARSEC workloads execution.
In second architeture, we propose a novel compression method called Zero-Duplicate Compression (ZDC) to compress network traffic and to increase lifetime in Non-Volatile Memories (NVMs) as a Last-Level-Cache (LLC). Moreover, we limit compression by a new mechanism called NoS to reduce delay overhead and static energy from compression/decompression. Our experiments show that the ZDC provides comparable compression ratio to two other state-of-the-art compression methods and the NoS improves energy consumption and performance by about 76% and 11%, on average, compared with the traditional architecture, respectively.
Keywords: Coding, Last Level Cache (LLC), Nonvolatile Memory (NVM), Network-on-Chip (Noc), Energy.
