چكيده به لاتين
Rhythmic patterns in human and animal bodies, whether vertebrate or invertebrate, are produced by a special group of neurons and synapses. These specialized neural networks which provide the rhythmic bursts of spikes that form the basis for all muscle contraction orders and locomotion are called central pattern generators. Nowadays, in order to find effective treatments for neurological disabilities and improvement of robotics technology, it is necessary to produce these patterns artificially with artificial central pattern generators. For simulating a central pattern generator, it is necessary to simulate neurons and synapses. Izhikevich model is used for simulating neurons. Differential equations for synapses and Izhikevich model are simulated in MATLAB. In the second place, a central pattern generator comprised of two neurons and two synapses is simulated in MATLAB. Hardware implementation of a central pattern generator requires silicon circuits for neurons and synapses. An analog circuit for implementing Izhikevich neuron is used to produce bursting patterns of neurons. A synapse circuit should save synaptic weight, change it and multiply the synaptic weight by the input of synapse circuit. Memristor characteristic helps us to optimally implement the synapse circuit.
Memristor or memory resistor is a passive element which its memristance is adjustable by the current passing through it while its memristance would be constant if its voltage is less than threshold voltage. In this case, memristor acts like a resistor. The proposed synapse circuit is designed in a way that it takes advantages of the memristor. The memristance is adjustable in a wide range and the voltage on the memristor while working is less than the threshold voltage. The proposed synapse circuit comprises two memristors, an input buffer and output current mirror. This circuit is validated by different synaptic weights which produced by changing the memristances of the circuit. By increasing the synaptic weight, the amplitude of the output signal rises. The final central pattern generator circuit is designed and simulated by CMOS neuron and memristor-based synapse. In the final circuit, the rate of output bursting patterns is changeable by adjusting the synaptic weight. By increasing the synaptic weight, the rate of producing bursting pattern rises and by decreasing the synaptic weight, the rate is reduced. In this regard, the period of bursting patterns is adjustable from 6 microseconds to 857 microseconds. In addition, the synaptic weight is adjustable from about 0.15 to 20000. Furthermore by considering different synaptic weight for each synapse, relative interval between output of neurons as changeable and we are able to adjust position of the outputs of the neurons. The CMOS circuit is designed and simulated in a 0.35μm CMOS technology.
