چكيده به لاتين
Abstract:
According to ITRS, using Three-Dimensional Chips for connecting processing elements, memory and I/O modules on chips that made with less than 65 nm technologies is One of the best solutions in construction of three-dimensional integrated circuits using of through-silicon-via (TSVs) strongly increase the Manufacturing cost of Three-Dimensional chips, so that the fabricating of a three dimensional network on chip with the total number of vertical links is not efficient because of cost and complexity of this process.
On the other hand, the problem of routing information in 3D NOCs in comparison with 2D NOCs is because of incompleteness of TSV channels. In this thesis, we propose a partially adaptive routing algorithm for vertically partially connected TSV links for three-dimensional network on chips. The proposed algorithm is divided network layers into four groups and for each layer of these groups, provided a routing strategy. Also rows and columns in each layer can be divided into two Odd and Even groups and routing strategies in rows and columns are different from each other. The proposed routing algorithm using two virtual channels in each layer is deadlock and livelock free and is evaluated using Access Noxim simulator, in which the proposed method is compared with the well-known Elevator_First algorithm. Our experimental results reveal that the average improvement of packet delivery latency of our algorithm significantly outperforms the Elevator_First algorithm with maximum of 54% and the average of 32.8%. Also network throughput in the proposed algorithm is better than Elevator_First. Moreover, evaluations show that diagonally placement of TSVs in layers in terms of improving average latency is the best scenario.
Keywords: Deadlock, 3D NOC, Partially Adaptive Routing, Partially Connected TSVs, Virtual Channel
