چكيده به لاتين
Abstract:
Trend toward using many IP’s in a single chip and simultaneous execution of tasks has been attracted designer’s attention to communications among IPs. Since networks on chip have lots of merits compared to other communication ways, this technology has been chosen as an appropriate communication infrastructure, But due to its complex nature created because of its architecture and application model diversities, its performance evaluation has been converted to a new challenge . Among various evaluation ways of network on chip performance parameters, analytical models have been popular duo to high execution speed, adequate insight on design parameters and acceptable accuracy.
In this thesis, we attempt to obtain an accurate, fast and comprehensive analytical model for performance evaluation of networks on chip. In this thesis, using queueing theory, we propose a delay model in a wormhole-switched network on chip with round-robin arbitration and different ratio of packet length and buffer size. Proposed model composed of two equivalent queue, open workload and closed workload. In this model, pipeline’s cycles which is heterogeneous duo to their event’s reason, have been homogeneous on the ways that don’t have wrong effects on real delay; Also duo to wormhole-switched, we consider transfer delay equal to the transmission time of a flit over one pipeline cycle. In the next step, we have paid attention to execution time of analytical model. Congruent link technique has been introduced to reduce execution time of analytical model. Using this technique, we can prevent calculation of all links parameters.
Experimental results on synthetic traffics show that our proposed model has good degree of accuracy and can improve horizontal error on average 20%. Experimental results also shows that congruent link technique can decrease execution time up to 50%.
Keywords: network on chip – analytical model – model execution time – queueing theory
