چكيده به لاتين
Carrier and clock synchronizers are one of the most important units in digital communication receivers. Digital communication receivers suffer from some destructing effects like phase noise, Doppler, channel effects, local oscillator mismatching, etc. Hence, the presence of an appropriate synchronizer in receivers is inevitable. A proper architecture is selected based on maximum acceptable transmission rate, transmission media, expected performance, etc. On the other hand, many of the relevant publications have focused on reconfigurable hardware platforms for implementing synchronizers at the receivers. FPGAs are used for implementing both feedforward and feedback structures in clock and carrier synchronizers.
In this thesis, at first a different approach is investigated to derive new feedforward NDA timing estimators based on Newton algorithm. Two novel estimators with four and two samples per symbol are presented and compared to traditional timing estimators, respectively. One of the main advantages of the second proposed estimator is the ability to control the loop gain automatically. This ability improves the convergence speed, variance of the error and robustness of the design. After that in the next chapter, an appropriate compensation method using a novel smith predictor is proposed to achieve good stability conditions in the presence of loop delay in synchronization loops. Since the delay compensation technique is applied, the proposed architecture is well suited for pipelined VLSI implementations. Also by using this modification, appropriate internal filters are employed in timing and carrier recovery loops while the delays of these filters are compensated.
In order to evaluate the effectiveness of the proposed design, two different scenarios are implemented on hardware platform. For the first scenario the multi-rate transmitter-receiver which has the ability to track high dynamic low SNR signals in wireless communications is presented. And in the second scenario, by utilizing speed optimization methods clock frequency of each sub-systems is increased and high speed digital MODEMs is designed and implemented. In these two systems some modifications by using digital Automatic Gain Control (AGC) to equalize the received signal, employing pre-filter to mitigate self-noise, utilizing coarse and fine phase estimation to improve the performance of the estimators, using phase-unwrapper unit to extend the linear range of the estimator, and etc. are applied in implemented design. Implementation results show that our design has a good performance for different modulation orders as well as excellent robustness against loop delays, low SNRs, high dynamics and variations in the loop.
