چكيده به لاتين
Abstract*
Today, hostile and malicious activities in integrated circuits (ICs) have become a great concern for digital system designers. This is mostly because of the globalization of designs to be fabricated. An adversary can introduce a Trojan to design to disable or destroy a system at some future time, or leak confidential information and secret keys.
Because of the fact HTs are inserted into the circuits by intelligent adversaries and are designed to have a minimum effect on chip's side channel characteristics, test patterns used detect manufacturing faults are not of much help. In recent years, many approaches have been proposed to address this.
In this thesis, one gate level method has been proposed to facilitate and improve HT detection. In this work we try to reduce circuit power consumption in test time to make HT effects on power side channel observable. The design will be divided to equal regions and then by inserting special logic gates in each partition we try to focus on each region’s dynamic power. By generating appropriate test patterns based on these regions and also added logic gates, it would be possible to activate each region in test time while keeping the rest of the circuit silent. Then by comparing power consumptions it would be clear either the circuit contains HT or not. In this thesis ISCAS’85 benchmarks have been used.
Key Words
Hardware Trojan Detection, IC Test, Side-Channel Analysis, dynamic power, obfuscation