چكيده به لاتين
In recent years, with the rapid development of microelectronics technology, implantable chips play an important role in medicine. In the meantime, neural signal recording micro-systems are important for understanding brain activity and helping to develop various algorithms for dealing with neurological diseases. These micro-systems have several units, each of which has its own design considerations and challenges. The first step in designing low-power and low-noise neural recording microsystems is to design the front-end section (which is considered as the main part of this dissertation). The front-end section of these microsystems includes several building blocks such as sensory circuits, analog multiplexers, and analog to digital converters. The proper design of each of these stages will have a very important role in overall system performance.
The neural sensory unit is one of the most important units of the neural signal recording microsystems. In these microsystems, the electrodes produce weak signals that need to be amplified, filtered, and buffered for further processing. In this work, a capacitive feedback network is used to implement the amplifier stage. Furthermore, due to the good trade-off between power consumption and input-referred noise in current reuse OTAs, these structures have been employed as the core of the proposed neural amplifier. Despite the numerous advantages of current reuse OTAs, these structures (like any other Class A structure) have limited power efficiency. In this doctoral dissertation, the power efficiency problem of the traditional current reuse structure has been substantially eliminated by using an innovative approach based on the adaptive biasing of the input pair (while maintaining the advantages of the current-reuse structures).
Another important part of a neural recording front-end is the multiplexer unit, and its proper design is one of the important goals of this doctoral dissertation. The primary issue in designing analog multiplexers is the precise operation of their analog switches. Channel charge injection and clock feedthrough effects are the most important characteristics that must be considered while designing analog MOS switches. These effects have been substantially reduced in the proposed switch by employing an innovative approach.
Another objective of this work is to develop a low-power ADC with the required specifications for neural recording applications. Among the various ADC structures, SAR ADCs are suitable to deal with neural signals in terms of the effective number of bits, power consumption, and bandwidth. In traditional SAR ADCs, the binary search algorithm is used to update the input voltage approximation based on the comparator output voltage. However, in LSB-first SAR ADCs, some modifications have been employed to significantly reduce the power consumption of the structure. In this way, the proposed ADC in this work is based on the LSB-first method.
Finally, electromagnetic compatibility (EMC) is another issue that should be considered while designing neural recording microsystems. All of the solutions to reduce the effect of the interference on the analog circuits can be divided into four general categories: 1) Attenuating the EMI signal at the input stage, 2) Linearizing the nonlinear devices, 3) Increasing the circuit bandwidth, and 4) Compensating the DC-level. Of the mentioned solutions, the last three items are implemented simultaneously in the proposed OTA structure and therefore the proposed OTA has a very good EMC performance. Also, the interference robustness is achieved without using excessive power and also the noise performance is not affected.
