چكيده به لاتين
By increasing the number of transistors per chip, reducing power consumption is among the essential requirements of electronic industry. Reducing power consumption requires reducing the supply voltage and sub-threshold leakage. Complementary Metal Oxide Semiconductor (CMOS) transistors cannot show progressive performance due to limitation in supply voltage scaling and sub-threshold slope (SS) limitation below value of 60 mV/dec at room temperature. Tunneling based Field Effect Transistors (TFETs) are emerged as alternatives for conventional MOSFETs due to steep sub-threshold slope and low leakage power.
In this thesis the main electrical characteristics of TFETs are improved by Methods such as using stacked gate oxide and metal implanted in the oxide on top of drain. Proposed stacked gate oxide by increasing electric field at source-chanel junction, which causes decreasing tunneling barrier width thereby, more electrons tunnel. As a result, ON current enhancement and improvement in sub-threshold slope are achived. Also, metal implanted by increasing tunneling barrier width and decreasing energy range capable of tunneling, which causes reduction in ambipolar current. Moreover, a 2-D analytical model of tunneling transistor is proposed in which drain current is computed by integrating band to band generation rate over the tunneling volume. In the following, the drain current is optimized for different silicon body thicknesses, different combinations of gate dielectric and different combinations of gate length ratios.
