چكيده به لاتين
Given the rapid growth in the number of small IoT devices, designing an encryption system based on the needs of IoT devices is limited in resources to provide end-to-end security.
This research presents a lightweight advanced encryption standard (AES) , a high-security symmetric encryption algorithm, performance on a programmable field gate array (FPGA), and 65nm technology for resource-limited IoT devices. This architecture includes an 8-bit data path and five main blocks. To store plain text, keys and intermediate data, two specified registration banks, Key-Register and StateRegister, are designed. To reduce the area, Shift-Rows are embedded inside the StateRegister. To adapt the Mix-Column to an 8-bit data path, an 8-bit block optimized for Mix-Columns with four internal registers is designed that accepts 8 bits and returns 8 bits. Also, a common optimization sub-byte is used for the key expansion phase and the encryption phase. To optimize sub-bytes, some sub-bytes have been merged and simplified. To reduce power consumption, the gate clock technique has been used. . The results of the Integrated Applications (ASIC) circuit implementation show a corresponding improvement from 35% to 2.4% compared to previous similar tasks. Based on the results, the proposed design is a suitable encryption system for small IoT devices.
