چكيده به لاتين
The sharp increase in the leakage part of the total power of the VLSI circuits is a significant concern in the deep sub-micron CMOS process. A novel input controlled leakage restrainer transistor (ICLRT) technique is proposed in this thesis to reduce leakage power as well as the short circuit power. The main idea is to place a PMOS and an NMOS ICLRT on top of the pull-up network (PUN) and at the bottom of the pull-down network (PDN), respectively on all paths from either the supply voltage or the ground to the output. The ICLRTs are deliberately used as a stack structure while being controlled by the input signals to lead the output to stronger low and high logic levels. In fact, the proposed technique reduces the leakage and short circuit currents and, consequently, powers by increasing the threshold voltage and decreasing the gate-source voltage of the main transistors. Using the proposed technique, logical NOT, NAND, NOR, XOR, and XNOR static gates are designed and evaluated by SPICE simulations in 22-nm BSIM4 (level-54 parameters) CMOS technology. Simulation results with 0.9-V power supply voltage show that power-delay product (PDP) is reduced by 27.66%, 16.7%, and 21.58% for NOT, NOR, and XOR with respect to its best counterpart and by 32.62%, 47%, 49.23%, and 38.77% for NOT, NAND, NOR, and XOR with respect to the conventional static-CMOS structures.
The full adders are vital parts in various VLSI circuits/systems, especially in circuits used for fulfilling arithmetic operations. Those are often placed in the critical paths for multiplication and division, so influence the throughout the efficiency of the system. To test the proposed technique, ICLRTs added to five best 1-bit hybrid full-adders in the deep sub-micron process to fit the needs of the day. evaluation outcomes with 1-V power supply verified that the power dissipation and power-delay product (PDP) of the hybrid full-adders based on ICLRT technique relative to corresponding original designs are reduced 65.67-95.7% and 35.85-87.37%, respectively. Also, ICLRTs are applied to four 4-2 CMOS compressors. Simulation results with 0.9-V power supply revealed that the power consumption of the 4-2 CMOS compressors based on ICLRT technique is reduced 59.62-74.28% and also power-delay product (PDP) is diminished 32-46.78% relative to corresponding original designs.
A self-control leakage-suppression block (SCLSB) for leakage power reduction of static CMOS gates is proposed in this thesis too. The proposed SCLSB consists of two PMOS and two NMOS transistors that are located between pull-down network (PDN) and pull-up network (PUN). In any combination of input signals, one PMOS and one NMOS transistor of SCLSB turn on and the rest turn off, hence the resistance between the power supply voltage rail to the ground rail increased and leakage currents greatly reduced. The basic static CMOS gates such as inverter, NAND, NOR, and XOR circuits are designed based on SCLSB. evaluation outcomes with VDD=0.9 V depict that power-delay product (PDP) is diminished by 9%, 12.8%, 6%, and 15.25% for inverter, NAND, NOR, and XOR compared to the best counterpart (LECTOR) and by 9%, 35%, 21.5% and 33.8% compared to the conventional CMOS gates.
Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the I-V characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this thesis, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors that the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies.
Although the field-programmable analog arrays (FPAAs) are faster, smaller, and lower consumed power with respect to digital counterparts, but their processing power and applications are bounded because existence few of configurable analog blocks (CABs) in each FPAA. Moving towards the analog integrated circuit (IC) design in deep-submicron technologies and increasing CABs numbers in each FPAA is a promising solution for relieving this shortage. Nevertheless, scaling down to nanometer CMOS technologies has severe short-channel effects for analog IC designers such as alteration of I-V characteristics of MOS transistors. A novel current-mode multifunction CAB is designed using LLDB-Ms that including a new low-leakage dual-translinear cell (LLDTC), PMOS/NMOS arrays and local switches. Three NMOS LLDB-Ms and three PMOS LLDB-Ms as well as eight current branches are building elements of a proposed LLDTC that are operating in weak inversion region. The proposed CAB based on the how insert the input current signals by branches is capable to implement the such various current-mode computational functions as two-quadrant squarer, four-quadrant multiplier/divider, vector-summation and true RMS to DC converter. Post-layout simulation results illustrate that the proposed circuit-level method by considerably reducing leakage currents could accurately realize the computational functions in deep-submicron technologies. Hence, a large number of these CABs together lead to an FPAA with high processing power and applications.
