زهرا شامي

Convolutional Neural Network (CNN) is one of the most influential deep learning algorithms in solving various problems, such as image processing. The high accuracy of CNN is achieved by complex computations, which have created many challenges in the design of its hardware units. In recent years, Field-Programmable Gate Arrays (FPGA) have been introduced as high-performance CNN accelerators with features such as reconfigurability, parallelization at different levels and energy efficiency. In this regard, High-Level Synthesis (HLS) tools play a significant role in facilitating the design of such accelerators. In this thesis, we have developed a targeted framework for designing a CNN hardware accelerator based on FPGA using HLS. The proposed architecture uses 15-bit data representation for input and network parameters. The data in the presented model is transmitted as streaming data. In the proposed model, the use of a novel algorithm for implementing the convolution layer has reduced memory access and consequently reduced power consumption. Additionally, parallelization at different levels and the use of pipelining techniques have resulted in reduced latency. The proposed architecture has high flexibility and by changing the hyperparameters, it can execute any CNN network containing convolution and max-pooling layers on this system. In this thesis, the proposed CNN accelerator was implemented on the Xilinx XC7Z020 FPGA and eva‎luated using the MNIST database. The accuracy of digit recognition by the proposed CNN model is 98.7% and the detection latency is 39,140 clock cycles at 100 MHz frequency. In the hardware implementation of this model, 3% of BRAM blocks, 23% of DSP48E slices, 50% of LUT resources and 15% of flip-flops available in the XC7Z020 FPGA are used. Comparing the results of this thesis with the related designs on the zynq 7000 chip for MNIST dataset shows at least a 2-fold improvement in the introduced FOM based on accuracy, latency, and hardware resource utilization.

شبكه‌ي عصبي كانولوشن , شتاب‌دهنده‌ي سخت‌افزاري , آرايه دروازه برنامه‌پذير ميداني زينك , ابزار سنتز سطح بالا

Convolutional Neural Network , Harddware accelerator , Zynq FPGA , High Level Synthesis

Zahr Shami

Dr. Mirzakuchaki