احمد توحيدي گل

Nowadays, energy efficiency has become a significant challenge in the design of processing hardware. In this research, approximate computing methods have been employed to design energy-efficient computational circuits. Approximate computing is a design paradigm that utilizes the flexibility and resilience of applications to errors in order to reduce the cost of hardware or software implementations. Considering the extensive usage of multiplier and accumulator units in signal processing and machine learning systems, this thesis proposes several approximate fixed-point and floating-point multiplier circuits. The proposed fixed-point multipliers in this thesis are of the dynamic range type. The accuracy of dynamic range multipliers is independent of the input operand range and they preserve circuit linearity in applications such as FIR filters. The floating-point format is designed to represent the wide range numbers. This feature of fixed-point numbers eliminates the need for auxiliary circuits in processing the dynamic range numbers. In this thesis, several approximate multiplier circuits for the floating-point format are proposed. To eva‎luate and compare the proposed multipliers, a figure of merit (FOM) metric based on the SAW method (Simple Additive Weighting) has been used. This metric enables the assignment of weights to attributes according to their significance. Three different approaches are considered for weighting the attributes. In the first approach, all attributes have equal weight, while in the second and third approach, a greater weight is assigned to power consumption attribute. The proposed multiplier designs demonstrate significant reductions in power consumption. The 16-bit approximate fixed-point pseudo-Booth multiplier, equipped with a radix-4 pseudo-Booth encoder and 12-bit truncation, achieves 89% reduction in power consumption compared to the exact multiplier. The MRED (Multiplicative Relative Error Distance) value of this multiplier is 4.2%. Similarly, the approximate floating-point pseudo-Booth multiplier, equipped with a radix-4 pseudo-Booth encoder and 4-bit data width, achieves a remarkable 98.9% reduction in power consumption compared to the 32-bit floating-point multiplier, while its MRED value is 3.2%. Furthermore, the more accurate iterative version of this multiplier, equipped with a radix-16 encoder and 19-bit data width, achieves a substantial 67.5% reduction in power consumption and remarkable MRED value of 8.5×10^(-4)%. In addition to the design and eva‎luation of approximate operators in different applications, this thesis also introduces a novel approach to approximate neuron design. The proposed neuron utilizes the sigmoid activation function and achieves remarkable improvements compared to its equivalent 16-bit precise neuron. Specifically, it provides a significant 43.2% reduction in power consumption.

محاسبات تقريبي , مدارهاي انرژي كارآمد , پردازش تصوير تقريبي , ياخته عصبي تقريبي

Approximate computing , approximate image processing , approximate neuron , low-power circuits

Ahmad Towhidy Gol

Karim Mohammadi