چكيده به لاتين
In recent years, System-on-Chip (SoC) technology has witnessed widespread adoption across various domains, including embedded systems, mobile phones, and hardware accelerators. As technological advancements continually sought to enhance the computational complexity of advanced applications, there arose a pressing need to augment processing speed. Consequently, researchers turned their attention to expanding the number of processing cores within SoCs. Concurrently, the imperative to reduce power consumption in battery-dependent systems and minimize the physical footprint in compact devices, such as mobile phones, gained significance. To address these challenges, Network-on-Chip (NoC) emerged as a scalable solution, supplanting conventional approaches like shared buses. Its deployment aimed to ameliorate issues related to latency, power consumption, and spatial efficiency in these systems. Furthermore, the evolution of chip technology, marked by the reduction in transistor dimensions, exerted a pivotal influence on power consumption and latency. Prior research on NoCs primarily concentrated on evaluating routing algorithms, security aspects, and network-on-chip router efficiency. However, despite the pivotal role played by chip technology advancements in shaping the characteristics of hardware components, particularly NoC routers, limited attention has been devoted to this aspect. Additionally, the absence of simulation-based evaluations in certain studies hints at a deficiency in accuracy. In essence, the routers, responsible for steering and governing data flow alongside the communication links interconnecting these routers, collectively constitute the NoC. This study aims to heighten researchers' awareness regarding the impact of advancing chip technology. To this end, we propose an evaluation of chip-based network routers across diverse chip technologies. Subsequently, we implemented these routers using synthesis tools and various chip technology libraries, unveiling disparities between simulation results and earlier predictions, such as a significant deviation of up to 73%, particularly in terms of the spatial footprint. Moreover, as part of the simulation, we scrutinized the delay characteristics of communication links connecting the routers. In addition to assessing network routers within a chip and the inter-router communication links, this research introduces a tool capable of automatically receiving hardware descriptions as input and synthesizing them across six distinct chip technologies. Subsequently, this tool generates and stores the corresponding graphical representations.
