چكيده به لاتين
In this thesis, the conventional single-stage comparator circuit has been analyzed, and dynamic two-stage comparator circuits have been designed and proposed to improve its performance. The conventional and proposed dynamic comparator circuits are implemented in Cadence software using 180nm CMOS technology for both pre-layout and post-layout designs. Although the conventional single-stage dynamic comparator has a simple design structure, it consumes a significant amount of current during the evaluation phase, particularly at low common-mode voltages. Furthermore, its input common-mode voltage range is limited, which is crucial for many applications, such as Successive Approximation Register Analog-to-Digital Converters (SAR ADCs).
The first proposed comparator, designed with an inverter-based pre-amplifier, improves delay and power consumption by more than 80% compared to the conventional single-stage comparator. The overall offset voltage of the circuit is slightly more than 10mV, and its variation across the entire input common-mode voltage range is less than 1.5mV. The layout area consumption is calculated to be 1080µm².
Next, to improve area consumption and offset voltage, the second proposed comparator, based on a thyristor, is introduced. The delay and power consumption of the thyristor-based dynamic comparator have been improved by 85% and 76%, respectively, compared to the conventional single-stage comparator. The overall offset of the comparator in the rail-to-rail common-mode range is below 9.32mV, with variations less than 2mV. Its layout area consumption is 517µm². While this circuit improves offset voltage and area consumption, its power consumption and offset variation in the input common-mode voltage range have increased slightly.
Finally, to improve power consumption and offset variation, the third comparator circuit has been designed, minimizing the aforementioned challenges. A dynamic biasing method has been used to prevent full charging of the pre-amplifier nodes, resulting in reduced power consumption and delay. Compared to the conventional single-stage comparator, dynamic biasing improves delay and power consumption by 86% and 80%, respectively. The overall offset voltage of the proposed circuit is below 10mV in a wide range of input common-mode voltages, with variations of less than 1mV.
