چكيده به لاتين
The Clock and Data Recovery (CDR) circuit is a key component in high-speed transceivers, extracting the clock signal from the incoming data stream and using it for data sampling. The implementation of these circuits faces challenges such as power consumption, frequency band interference of the phase and frequency detector, and the need for multiple phases for frequency detection.
In this thesis, reported structures in the literature have been reviewed, and finally, a suitable structure for design has been proposed. The CDR structure is designed in such a way that phase and frequency adjustment is performed in a single loop using only two clock phases. This leads to circuit simplification, suitability for subsurface systems, reduced power consumption, and minimized chip area.
The received data in the receiver system is recovered using the CDR circuit, where Phase-Locked Loops (PLLs) play a crucial role. Among PLLs, the binary phase-locked loop is preferred for high-frequency applications due to its high gain. Additionally, several logic circuits are utilized to design the frequency detector block. This approach aims to reduce the occupied chip area and power consumption, particularly in implantable medical devices.
Furthermore, a high-speed CDR circuit with a data rate of 1.76 Gbps has been designed and simulated. The overall system consists of multiple components, with the most critical part being the phase and frequency detector circuit. This thesis introduces a novel frequency detection method that significantly reduces power consumption and chip area while simplifying the clock recovery unit design.
Finally, a low-power CDR circuit in 180nm CMOS technology, including phase and frequency detectors, charge pump, first-order low-pass filter, and oscillator, has been designed and simulated using Cadence software. The total power consumption of the CDR circuit is 2 mW, and the supply voltage is 1.8V.
