سيدپرهام محسني

Abstract: Processor is one of the core components of digital circuits, performing computational operations using memory an‎d data flows. Processor architectures define the structure an‎d method of executing instructions. The RISC architecture, instead of a large set of complex instructions, employs a small an‎d simple set of general-purpose instructions. This approach not only simplifies the design but also optimizes speed an‎d energy consumption. In this project, the aim is to assess the security of the BOOM processor, which is an out‑of‑order execution core based on the RISC‑V architecture. To this end, a set of security attacks—including timing attack, code injection, ROP chain, return‑to‑libc, data‑only attack, an‎d privilege escalation—were implemented an‎d simulated. For quantitative eva‎luation, metrics such as attack success rate, number of semi‑successful an‎d failed attacks, overall performance, average clock cycles, an‎d average power consumption were measured. For qualitative eva‎luation, the three core security principles—confidentiality, integrity, an‎d availability—were analyzed, an‎d the most vulnerable configurations were identified. The results showed that some configurations, such as PINK, had low overall performance (10%) an‎d consequently the highest number of successful attacks (1000 cases), whereas configurations such as TAGE, with high overall performance (89%), demonstrated greater resilience against certain attacks. Keywords: Processor, RISC Processor, RISC‑V Processor, BOOM

پردازنده , پردازنده RISC-V , پردازنده بووم

Processor , RISC‑V , BOOM

parham mohseni

dr.sattar mirza kuchaki