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RecordNumber
25617
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Title
Cache and interconnect architectures in multiprocessors
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Author Statement
Edited by Michel Dubois and Shreekant S. Thakkar
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Publication
Kluwer Acad
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Publication Year
1990
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Collation
xii, 277P., illus., diags., tables
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Notes
0792390741 , Includes bibliographical references , Papers presented at a workshop titled Cache and Interconnect Architectures in Multiprocessors, held in Eilat, Israel, May 25-26, 1989
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Subject
Computer network architectures , Multiprocessors , Computer network protocols
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ADDED ENTRIES
Thakkar, S. S. , Dubois, Michel ,
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LC Class
TK
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LC Number
5105.5
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LC CutterNumber
.C33
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Link To Document :
