چكيده به لاتين
Abstract
Due to the decreasing of transistors size, there is a possibility for implementing many-core processors. In this trend, the amount of leakage and dynamic power consumption has been increased. In the nanometer era, there is not possibility for providing the required power budget of these platforms. Based on ITRS predictions, in 22nm technology, in 2014, about 21% of the chip will be turned off and in 8nm technology, in 2018, more than 50% of the chip will be turned off. This challenge has been named to “dark silicon” phenomena. Increasing power consumption not only leads to increase cost and dark area, but also leads to increase of chip temperature. Increasing of chip temperature and creating hot spots leads to reliability problems in the chip and reducing chip life time. In this regard, some architectures and techniques have been proposed for power management to reduce dark area in multi/many core systems.
Memory modules and cache banks are the important components of on-chip storage and have big portion in total chip-multiprocessor (CMP) power consumption. Emerging Non-volatile memory (NVMs) technologies with desirable characteristics such as near-zero leakage power, high density and etc. in comparison to the traditional technologies are ideal for using in next-generation CMPs to combat dark silicon.
In this thesis, after surveying and defining the problem in future CMPs design, we study on NVM technologies and their advantages and disadvantages. In continue, we propose an energy-efficient reconfigurable hybrid last level cache architecture for future CMPs. In this proposed hybrid architecture SRAM memory is incorporated with STT-RAM technology for using the advantages of both new and traditional technologies.
Keywords: Last Level Cache (LLC), Non-Volatile Memory, Power Consumption, chip Multi Processors (CMPs)
