چكيده به لاتين
In nanometer dimensions, increasing the memory cell leakage power have caused the standby power of SRAM on-chip caches to dominate the overall power consumption of the future multi/many cores. With continuous technology scaling the efficiency of circuit design and architectural solutions to decrease the standby power of SRAM caches is reduced.To address this issue, the employment of emerging non-volatile memory as a replacement has been proposed.STTRAM magnetic memory technology isa very promising candidate to be universal memory due to its superior scalability, zero standby power and robustness against radiation. Having a cell area much smaller than SRAM, magnetic memory can be used to construct much larger cache with the same die footprint, leading to significant improvement of overall system performance and power consumption especially in this multi-core era. However, STTRAMs have some drawbacks such as high write energy and write latency,limited endurance andread disturbance, that need to be overcome for feasible deployment of STTRAM caches. Reducing the retention time of STTRAM cells is known as a way to decrease power consumption and improve the write performance. On the other hand, the enhancement in write performance results in the degradation of read operations, in terms of both speed and data reliability.In this thesis, a cache layer design that combines memory banks with different retention time for a three-dimensional multiprocessor has been proposed. To this end, an optimization model to find the optimal configuration memory banks is used. The goal is to provide tradeoff between reliability, power consumption and improve performance accordingly. Simulation results from PARSEC benchmarks through comparison with pure SRAM and pure STTRAM cache architectures show that the proposed cache architecture reduces the power consumption and occupation area,while also increasing the performanceon average up to 25 percent.
