چكيده به لاتين
As multicore systems shift to many-core realm, transistors’ parameters, as well as interconnect parasitics play a pivotal role in circuit design. Variability, power consumption, and circuit complexity are of the most important impediments for successful state-of-the-art circuit design. High-speed requirement makes the on-chip global interconnects a major bottleneck in modern system on chips (SOC’s).
There are different ways for boosting the speed of buses and long on-chip links. Employing repeaters and regenerators are of solutions for increasing the speed of data transfering on long links. However, in some applications such as queues in processors and routers in SOC’s, high throughput rate is needed.
In the first part, we present a mixed design of Low-Swing scheme and Self-Timed Regenerator (LS-STR) for elevating the speed of data transferring on long global interconncets. Our novel design has been simulated for transfering data along a 10-mm interconnect line. Comparing with repeater scheme, the propagation delay is reduced by 39.1% for iso-power. Also, up to 23.2% power reduction is achieved for iso-delay mode. Moreover, energy-delay product for iso-delay and iso-power is reduced by 21.5% and 31%, respectively. Finally, the occupied area is reduced by 36.3%. Using a statistics method, we have analyzed the reliability of the circuit considering process and power supply rail variations, and inter-line crosstalk noise. The LS-STR improves Signal to Noise Ratio (SNR) by 3.7% compared with STR design.
In the second part, a new class of synchronous elastic pipelines is proposed, called Dynamic ELastic Pipelines (DELPs), which employ dynamic logic family and achieve improved throughput and elasticity. The well-known PS0 style, proposed by Williams and Horowits, as well as conventional synchronous Static ELastic Pipeline (SELP) are used as the starting point, yet achieve remarkable improvements through novel control circuit optimizations. Two new single-rail and dual-rail pipelines are proposed. Post-layout simulations reveal that the proposed dual-rail DELP design has 19.1% higher throughput (2.12 giga data items per second) than that of Williams’ PS0 design, while the novel single-rail DELP design gains even higher throughput (3.2 giga data items per second). Also, the proposed single-rail pipeline reduced the occupied area and energy per data item by 23.6% and 17.4%, respectively.
Finally, all the proposed designs are simulated using CMOS 90-nm technology at 1.0 V power supply.
