چكيده به لاتين
The increase in the number of cores in embedded chip multiprocessors (CMPs) comes with an increase in transistor density on the chip and increase in the power consumption. However all of on chip components cannot be simultaneously powered on or utilized within the peak power and temperature budgets for sub-micron architecture. This phenomenon has been termed as the dark silicon era. Prior studies have proposed energy-efficient core designs to address the “dark silicon” problem. Nevertheless, the research for addressing dark silicon challenges in uncore components, such as shared cache, on-chip interconnect, etc., that contribute significantly on-chip power consumption is largely unexplored. So designing power/energy management techniques on uncore components especially on the shared last level cache and networks on-chip is essential in dark silicon era. Non-volatile memory (NVM) technologies such as Spin transfer torque RAM (STT-RAM) are emerging as promising candidates of memory architecture due to their attractive properties such as near-zero leakage power, high density and non-volatility. STT-RAM is considered as an attractive replacement for traditional memory technology for future CMPs in the presence of dark silicon. The increase in the number of cores in CMPs come with an increase in TSV counts. The TSV overhead such as area, manufacturing cost, thermal stress, temperature and yield loss, can increase significantly, with increase in the number of TSVs, so it is not functional to place numerous TSVs on a chip.
In this thesis, we propose a convex optimization based approach for designing an optimized 3D NoC and heterogeneous hybrid memory system for CMP by optimum placement of uncore components which contain eDRAM banks, STT-RAM banks and TSVs. STT-RAM suffer from high write energy and eDRAM banks need to refresh periodically that consume large portion of energy. The goal of the proposed architecture is to design a single structure that utilizes benefits of both technologies, while eliminating disadvantages and also minimizing energy of system, with minimum degradation on system performance while mitigate the dark silicone issue. Experimental results on PARSEC benchmark show that the proposed method improves energy-delay product (EDP) by 51% on average with 6% improvement of IPC compared to eDRAM structure and 20% degradation of IPC compared to STT-RAM architecture.
