چكيده به لاتين
Today, CMOS technology is the dominant semiconductor technology for microprocessors, memories and application specific integrated circuits (ASICs). Some disadvantages of this technology include: long reboot latency of programmable circuits, data loss during unexpected power supply interruptions and high leakage currents, especially when the technology scales to 100 nm and below.
In order to improve the reboot speed, data security and reduce energy dissipation, recently, the design and implementation of circuits using nano-scale magnetic cells is highly regarded. Nano-scale magnetic cells such as MTJs (Magnetic Tunnel Junction) are tiny, fast, programmable, non-volatile, and compatible with semi-conductor elements. They also dissipate zero static power and can be rearranged.
These special features have made MTJs a possible substitute for future logic devices and memories. Accordingly, by considering nano-scale magnetic cells as an effective substance for the reduction of occupied area and static power consumption, this research proposes two structures for designing and developing logic gates. The first proposed method, combining a reference resistance and parallel non-volatile elements, can generate all kinds of logical gates. The second proposed method, using only two non-volatile elements and a control current, not only can generate all kind of gates but also provide significant reliability and reduce the occupied area. The first proposed
method uses more elements than the second proposed method, but its power consumption is lower. The second proposed method is applicable in such applications in which the area is more important than the power consumption, while the first proposed method is applicable in such applications in which the power consumption is more important. The result of the experiments show that the proposed methods reduce energy at least 11% and increase reliability at least 50% .
