چكيده به لاتين
Reconfiguration overhead is one of the main obstacles in increasing speed performance in dynamically reconfigurable Field-Programmable Gate Arrays (FPGA), sometimes consuming more than half of time needed to execute a task. If it is recognized and forecasted correctly, a task can be preserved on FPGA’s surface after it has finished, in order to be used again if repeated in the future. In this thesis, an approach for reusing a repetitive hardware task in 2- dimensional hardware is proposed. At first, incoming tasks are divided into significant and non-significant task groups based on their features using fuzzy logic controller. Each group is placed in a specific partition of hardware and several methods such as replacement of significant tasks, using empty spaces in other partition, changing the partition border and trying to maintain border’s place, repetition ratio approximation and dynamic threshold for task significance are applied to reduce the rejection ratio. A simulation environment has been made to evaluate the algorithm’s performance and to make comparison with other state-of-the-art algorithms in this field which considers lots of necessary features like grouping tasks to simulate task dependency, rejection penalty, performance evaluation and etc. Conducted simulation shows that in repetitive programs, the proposed method has %15 less makespan and decides more than %70 faster than state-of-the-art algorithms in this field.
