چكيده به لاتين
In this thesis, a controllable current comparator is proposed. In proposed current comparator, resolution of current comparator is adjusted by changing the current source. Controllability is the most important innovation of this structure. For the first time, in the proposed structure, the required resolution is controled by adjustable structure, and with this innovation, power consumption is also reduced.
Proposed current comparator includes a current preamplifier and a current latch. The current preamplifier amplifies input current and decreases kickback noise while the current latch reduces response time. Simulation results are obtained by using cadence and 0.18 μm CMOS technology with 1.8 supply voltage. Simulation results shows propagation delay 242 ps in 500MHz with power dissipation 148.4 μw. As a unique feature, this current comparator can sense 1nA in 500MHz frequency. The pre-layout plus Monte-Carlo simulation results shows 235.6ps propagation delay time and the post-layout plus Monte-Carlo simulation results show 329.88ps propagation delay time. Finally, the proposed controllable current comparator is compared with previous current comparators that proves its significantly improved performance over the previous artworks.
Keywords: current comparator, controllable, preamplifier, current latch, kickback noise
