چكيده به لاتين
Sorting is a traditional data processing technique, used in various applications. Implementing hardware accelerators along with using full memory bandwidth, has gained extensive attention from research community. Application-specific integrated circuits (ASIC) and field-programmable gate arrays (FPGA) are preferable for implementing several Parallel Hardware Sorting Architectures (PHSA). Bitonic sorting is a parallel comparison-based sorting network, which is used in many hardware implementations. Number of Compare-And-Swap (CAS) blocks determines the amount of resources used in a Bitonic network. By increasing the number of input records in a sorting network, the number of CAS blocks will increase as well, which leads to a rise in resource consumption. The frequency also decreases, due to the increase in the number of steps in the Bitonic sorting. Schedulers often sort their task queues, depending on their scheduling policy. In Real-Time systems, it is preferable to have a constant time for sorting operations, so Scheduler should know the worst execution time. This paper proposes a novel approach for PHSA, in which a set of partial sorters sorts the input records to approach a constant time. The sorting time is almost constant, even if input records are increased, which is suitable for Real-Time applications. The results show that the number of LUTs of the proposed method has decreased by 70.2% and 87.3% compared to the Conventional Bitonic Sorting Network (CBSN) and the state-of-the-art PHSA, respectively. Also, the number of registers of the proposed method has decreased by 94.8% compared to the state-of-the-art PHSA.
