چكيده به لاتين
Abstract:
The flash analog-to-digital converter (ADC) is known as the leader type of ADCs in terms of speed. However, as the major weakness, it suffers from both large required chip area and power consumption that are exponentially increased with the resolution. To solve this problem, in this thesis, the novel greatly effective method of multi-segment encoding is introduced. In this method, a (2N-1)-to-N encoder is replaced by m numbers of (2Lm-1)-to-Lm ones. Each segment of multi-segment encoder, produces some of the bits of the ADC and finally a Latch bank, latches all of the bits. Both the number of inputs and outputs of each segment of the proposed encoder are fewer than the number of them in a conventional encoder. Hence, to remove the bubble errors and metastability, the complicated algorithms which increase power consumption and required chip area and decrease the speed, aren’t needed. So the structure of the proposed encoder especially in high-resolution and high-speed flash ADC is simpler and the FOM is better than other artworks. Also, the more segments in the multi-segment encoder would lead to its higher efficiency. In addition, by increasing the segments of the proposed encoder, the number and power consumption of the comparators latchs are decreased. In this thesis, a general-purpose, a high precise and an ultra-wideband flash ADC with a multi-segment encoder are designed and simulated in TSMC 0.18 µm CMOS technology. The FOM results of simulations are as follows (the reported FOMs are based on pJ/conversion-step): 0.317 in a 6-bit 1.5GS/s general-purpose flash ADC with a conventional encoder, 0.225 in a 6-bit 1.5GS/s general-purpose flash ADC with two-segment encoder, 0.186 in a 6-bit 1.5GS/s general-purpose flash ADC with three-segment encoder, 0.146 in a 6-bit 2.3GS/s ultra-wideband flash ADC with three-segment encoder and 0.257 in a 8-bit 1.5GS/ precise flash ADC with three-segment encoder. Therefore, impressive efficiency of the multi-segment encoder in operation of the flash ADC is confirmed. Most of the stated simulations are done with HSPICE while CADENCE is used just for shematic and post-layout simulations in a 6-bit 1.5GS/s general-purpose flash ADC with three-segment encoder.
Keywords: ADC, Flash, Low power, Multi-segment encoder, MCML, Multiplexer.
