چكيده به لاتين
With ever-increasing rate of scaling down the semiconductor devices, the SRAM based Last-Level Caches (LLC) have lost their efficiency due to a number of problems such as: Low Scalability, High Leakage Power and High Vulnerability to Soft Errors. Among the emerging memory technologies, Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) due to its extremely low leakage power and high density for integration compared to SRAM technology, is the most promising alternative for on-chip SRAM based LLCs. However, STT-MRAMs suffer from a few problems which could undermine their reliability. High write error rate due to the stochastic behavior of STT-MRAM memories, is the major reliability challenge of STT-MRAM based caches. Using Error Correcting Codes (ECC) is one of the most prevalent methods to reduce the write error rate in caches. However, since in most of the cases, effect of the memory contents on write error is overlooked, this method imposes a considerable overhead to the system in terms of energy consumption and performance. In this work, in order to reduce the write error rate in LLCs, we propose a new content aware replacement policy and architecture for each of the level one and LLC caches. The simulation results show that, our proposed method reduces the write error rate in the LLC by, up to 36% while it imposes less than 1% performance overhead to the system.
