چكيده به لاتين
This thesis presents two new structures in the design of Ultra wideband Low Noise
amplifiers. Due to low power consumption and high data transfer rates, the broadband standard
has become increasingly popular in the consumer market. The low-noise amplifier is the closest
block in the radio frequency receiver structure to the antenna. One of the tasks of low noise
amplifier is to provide sufficient power gain to amplify the received signal and apply the lowest
noise and distortion to this signal and move it to the next class (frequency Mixer).
The project designed and simulated two-structure of ultra-low-bandwidth amplifier in
180nm TSMC RFCMOS technology, and finally layout and Post-layout simulations were
performed in CADENCE too. Proposed structure 1 has a 2-3 dB Noise Figure, a maximum
Power Gain of 26dB, and gain variation was less than 3dB in whole the 3.1-10.6 GHz
bandwidth. This structure has a suitable impedance matching at the input and output and
optimum linearity (IIP3 = 12.9 dBm) using the DS Linearization approach over the desired
bandwidth. The designed structure number 1 has a power consumption of 35 mW at the voltage
of 1.8 V power supply with two floors with a common source-input class and simultaneous use
of a first class auxiliary transistor to improve the linearity of the amplifier structure. Proposed
structure 2 is also designed, simulated, layout and Post-layouted in CADENCE IC in the same
technology as structure 1. Structure number 2 has the similar topology with Structure 1,
designed to improve amplifier linearity in the 16-26GHz bandwidth. This structure has a
maximum transmission power of 10dB, NF of 3-4dB, a power consumption of 11.64mW and
a linearity index of 9.4dBm.
Keywords: Ultra Wideband Low Noise Amplifier, Linearization, TSMC RFCMOS
180nm Thechnology and CADENCE IC.
