چكيده به لاتين
Reduction in transistors size and approaching to VLSI nano-designs lead to significant increasing in power density and leakage power. Exponential increasing in power density leads to significant increasing in chip temperature. In this context, exponential increasing in temperature has negative impacts on chip reliability, power, and performance. In addition, with progressing of next-generation applications and increasing of their need to high-performance processors, architecture of processors has developed from single core to manycore. Researches have shown that more than thousand of cores will be integrated on a chip until 2030. This manycore integration on a chip trend leads to increasing in on-chip integrated transistors density and on-chip power density that increases operational temperature.
Memory modules, on-chip storages, and cache banks that are fundamental components in systems-on-chip (SoCs) architecture have a significant contribution in total chip power consumption. In manycore processors as well-known SoCs, integration of many cores on a chip leads to increasing in size of required cache banks to provide enough memory bandwidth and combat to memory wall. Leakage power consumption that is one of the major factors in increasing of chip power density and temperature is the main contributor in total power consumption of current memory technologies. Emerging of new memory technologies such as non-volatile memories with near zero leakage power and high-density characteristics in compared to current memory technologies are an ideal candidate in future manycore processors. In addition, these emerging technologies are good choices to combat to dark-silicon phenomena. In the first part of this thesis, to reduce the energy consumption in manycore chip-multiprocessors (CMPs), a hybrid integration of current and emerging memory technologies has been used to architect an optimal cache architecture. In hybrid architectures, emerging and current memory technologies are integrated to use the advantages of both technologies. In the second part of this thesis, a run-time technique with a negligible hardware overhead has been proposed to architect a low-power reconfigurable cache in future heterogeneous CMPs. In the last part of this thesis, a low-power uncore architecture including last-level cache (LLC) and network-on-chip (NoC) with applying an encryption method has been proposed. The target of applying this encryption method in the proposed uncore is reducing of write operations on last-level cache and on-chip traffic.
