چكيده به لاتين
In the past decade, distributed and multi-stage IC manufacturing paradigm gains more attention with the aim of reducing manufacturing costs as well as time to market. This paradigm provides an opportunity for attackers with malicious aims to impact the chip manufacturing chain. The emergence of the Hardware Trojan (HT) threatens the security of a computer system, which was traditionally assumed to be related only to the software or information being processed. Hardware Trojan attacks, in the form of malicious modification of an integrated circuit in its life cycle, create major security challenges in the electronic industry. These attacks cause operational failure on military devices or secret information leakage from inside a cryptographic chip. HT detection mechanisms, generally based on side-channel analysis and logic testing approaches, are presented by the researchers. Side-channel analysis approaches have limitations on detecting small trojans due to their vulnerability to process variation noise and sensivity to measurement accuracy of the target’s physical characteristics. Logic testing based solutions on the other hand try to generate test vectors with the objective to exciting rare trigged nodes of the circuit which limits their ability to find big trojans.
In this thesis, a logic testing based hardware trojan detection framework is presented to cover above mentioned limitations. The framework consists of two main stages which in the first, all nets of a circuit under test are investigated using innovative Hardware Trojan Susceptibility (HTS) model which is inspired from SCOAP testability parameters. Then, nets which are most suspected to be the main trigger of an HT are extracted using a specific interval partitioning algorithm. In the second stage, the extracted nets are passed to an HT excitation algorithm. The algorithm analyzes fan-in and fan-out cones of the nets to find subsets of them which are most probably, connected to an HT trigger circuitry. The excitation algorithm then tries to simultaneously excite all nets of a selected subset to their suspicions value and propagate the effects of excitation to the primary outputs of the circuit. The proposed framework is evaluated using two famous HT infected benchmarks, TRIT and Trust-Hub. The results show that an average of 90% of HTs inserted in these circuits of activated and the average HT activation time is about 100 times lower than famous method of this context.
