ميلاد كلوندي

The Data Processing Unit (DPU), as a new generation of programmable processors, plays a crucial role in modern data centers, complementing CPUs an‎d GPUs. By combining multi-core central processors, high-performance network interfaces, an‎d flexible acceleration engines, these units provide high-speed an‎d efficient data processing an‎d transfer. This thesis investigates the design an‎d implementation of an FPGA-based DPU utilizing modern technologies such as PCI Express an‎d DDR memory. These technologies enable high-speed communication an‎d complex data exchange in embedded systems an‎d data centers. In addition to their applications, the advantages an‎d disadvantages of DPUs have been analyzed. Benefits such as increased efficiency in cloud processing, improved data security, an‎d programming flexibility are discussed in detail. Furthermore, technical challenges like high acquisition an‎d maintenance costs an‎d the complexity of developing these units are addressed. In the second part of the thesis, the AES encryption algorithm, one of the stan‎dard an‎d reliable data encryption algorithms, is examined with a focus on its pipelined implementation on an FPGA. Various AES architectures, including looped, fully unrolled, an‎d deep pipelined types, are introduced an‎d their performance compared. Finally, by employing optimization techniques such as clock gating, a throughput of up to 6 Gigabits per second has been achieved on the FPGA, demonstrating the high efficiency of the design. The Cryptographic Avalanche Effect has also been confirmed to eva‎luate the security of this implementation.

واحد پردازش داده

PCIe , DDR , FPGA , AES encryption , Data accelerator , Data center

Milad Kalvandi

Dr. Sattar Mirzakuchaki